PD IEC TR 61189-5-506:2019 - Test methods for electrical materials, printed boards and other interconnection structures and assemblies. General test methods for materials and assemblies. An intercomparison evaluation to implement the use of fine-pitch test structures for surface insulation resistance (SIR) testing of solder fluxes in accordance with IEC 61189-5-501

PD IEC TR 61189-5-506:2019

Test methods for electrical materials, printed boards and other interconnection structures and assemblies. General test methods for materials and assemblies. An intercomparison evaluation to implement the use of fine-pitch test structures for surface insulation resistance (SIR) testing of solder fluxes in accordance with IEC 61189-5-501

Status : Current   Published : July 2019

Format
PDF

Format
HARDCOPY



IEC TR 61189-5-506:2019(E) is an intercomparison supporting the development of IEC 61189-5-501 in relation to the SIR method. This document sets out to validate the introduction of a new 200-µm gap SIR pattern, and was benched marked against existing SIR gap patterns of 318 µm and 500 µm.




Standard NumberPD IEC TR 61189-5-506:2019
TitleTest methods for electrical materials, printed boards and other interconnection structures and assemblies. General test methods for materials and assemblies. An intercomparison evaluation to implement the use of fine-pitch test structures for surface insulation resistance (SIR) testing of solder fluxes in accordance with IEC 61189-5-501
StatusCurrent
Publication Date18 July 2019
Normative References(Required to achieve compliance to this standard)No other standards are normatively referenced
Informative References(Provided for Information)IEC 60068-2-20:2008, IEC 61189-5-501
International RelationshipsIEC TR 61189-5-506:2019
DescriptorsSoldering fluxes, Evaluation, Structures, Printing board, Test methods
ICS31.180
CommitteeEPL/501
ISBN978 0 539 00068 9
PublisherBSI
FormatA4
DeliveryYes
Pages26
File Size5.097 MB
Price£182.00


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