IEC TR 62856:2013 - Documentation on design automation subjects. The Bird’s-eye View of Design Languages (BVDL)

IEC TR 62856:2013

Documentation on design automation subjects. The Bird’s-eye View of Design Languages (BVDL)

Status : Current   Published : August 2013

Format
PDF

Format
HARDCOPY



IEC/TR 62856:2013 describes features for existing design languages, as well as for enhancing and newly developing design languages belonging to the defined design processes of System on a chip (SoC) which ranges from system level design, SoC design implementation and verification, IP block creation and analog block design down to interface data preparation for manufacturing. Thirty-three design languages have been chosen and each feature of their latest version as of March 2011 is reflected in this report:


UML, Esterel, Rosetta, SystemC, SystemC-AMS, IBIS, CITI, TouchStone, BSDL, System Verilog, VHDL, Verilog HDL, UPF, CPF, e language, PSL, FSDB, SDC, DEF, Open Access, SDF, GDS II, OASIS, STIL, WGL, Verilog-A, Verilog-AMS, SPICE, VHDL-AMS, LEF, Liberty, CDL and IP-XACT.




Standard NumberIEC TR 62856:2013
TitleDocumentation on design automation subjects. The Bird’s-eye View of Design Languages (BVDL)
StatusCurrent
Publication Date07 August 2013
Normative References(Required to achieve compliance to this standard)No other standards are normatively referenced
Informative References(Provided for Information)No other standards are informatively referenced
ICS25.040.01
35.240.50
CommitteeEPL/501
ISBN978-2-8322-1028-4
PublisherIEC
FormatA4
DeliveryYes
Pages46
File Size1.348 MB
Price£116.00


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