BS IEC 62530:2011 - SystemVerilog. Unified hardware design, specification, and verification language

BS IEC 62530:2011

SystemVerilog. Unified hardware design, specification, and verification language

Status : Current   Published : July 2011



IEC 62530:2011(E) Provides a unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL. This publication has the status of a double logo IEEE/IEC standard.

Standard NumberBS IEC 62530:2011
TitleSystemVerilog. Unified hardware design, specification, and verification language
Publication Date31 July 2011
Normative References(Required to achieve compliance to this standard)IETF RFC 1321:1992, IETF RFC 2437:1998, FIPS 46-3:1999, IEEE Std 1364:2001, IETF RFC 2144:1997, IEEE Std 1364:1995, FIPS 180-2:2002, IEEE Std 1800:2005, IEEE Std 1364:2005, IETF RFC 2440:1998, IETF RFC 2045:199, FIPS 197:2001, ANSI Std X9.52-1998, IEEE Std 1003.1, IEEE Std 754, IETF RFC 1319:1992, IEC 62530:2007, ISO/IEC 10118-3:2004
Informative References(Provided for Information)IEEE Std 1497-2001, ISO/IEC 9899:1999
ReplacesBS IEC 62530:2007
International RelationshipsIEC 62530:2007,IEC 62530:2011
DescriptorsProgramming languages, Data processing, Interfaces (data processing), Data representation, Semantics, Electronic equipment and components, Syntax, Computer programs, Data transfer, Computer hardware, Verification, Design, Data
ISBN978 0 580 75663 4
File Size10.3 MB

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