BS EN 60191-6-20:2010 - Mechanical standardization of semiconductor devices. General rules for the preparation of outline drawings of surface mounted semiconductor device packages. Measuring methods for package dimensions of small outline J-lead packages (SOJ)

BS EN 60191-6-20:2010

Mechanical standardization of semiconductor devices. General rules for the preparation of outline drawings of surface mounted semiconductor device packages. Measuring methods for package dimensions of small outline J-lead packages (SOJ)

Status : Current   Published : December 2010

Format
PDF

Format
HARDCOPY



IEC 60191-6-20:2010 specifies methods to measure package dimensions of small outline J-lead-packages (SOJ), package outline form E in accordance with IEC 60191-4.




Standard NumberBS EN 60191-6-20:2010
TitleMechanical standardization of semiconductor devices. General rules for the preparation of outline drawings of surface mounted semiconductor device packages. Measuring methods for package dimensions of small outline J-lead packages (SOJ)
StatusCurrent
Publication Date31 December 2010
Normative References(Required to achieve compliance to this standard)EN 60191-6, EN 60191-4, IEC 60191-6, IEC 60191-4
Informative References(Provided for Information)No other standards are informatively referenced
International RelationshipsIEC 61937-14:2017,IEC 60191-6-20:2010,EN 61988-4:2007,EN 61937-14 Ed 1.0,EN 60191-6-20:2010
Draft Superseded By08/30190026 DC
DescriptorsSurface mounting devices, Electronic equipment and components, Printed-circuit boards, Engineering drawings, Standardization, Electric connectors, Semiconductor devices, Drawings, Dimensions, Integrated circuits
ICS31.080.01
Title in FrenchNormalisation mécanique des dispositifs à semiconducteurs. Règles générales pour la préparation des dessins d'encombrement des boîtiers pour dispositifs à semiconducteurs pour montage en surface. Méthodes de mesure pour les dimensions des boîtiers à sortie en J (SOJ) de faible encombrement
Title in GermanMechanische Normung von Halbleiterbauelementen. Allgemeine Regeln für die Erstellung von Gehäusezeichnungen von SMD-Halbleitergehäusen. Messverfahren für Gehäusemaße von kleinen Gehäusen mit J-förmigen Anschlüssen (SOJ)
CommitteeEPL/47
ISBN978 0 580 64566 2
PublisherBSI
FormatA4
DeliveryYes
Pages16
File Size1.166 MB
Price£130.00


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