BS IEC 62530:2007 - Standard for SystemVerilog. Unified hardware design, specification and verification language

BS IEC 62530:2007

Standard for SystemVerilog. Unified hardware design, specification and verification language

Status : Revised, Withdrawn   Published : December 2007 Replaced By : BS IEC 62530:2011

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Specifies extensions for a higher level of abstraction for modeling and verification with the Verilog hardware description language (HDL). This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI)>




Standard NumberBS IEC 62530:2007
TitleStandard for SystemVerilog. Unified hardware design, specification and verification language
StatusRevised, Withdrawn
Publication Date31 December 2007
Withdrawn Date31 July 2011
Normative References(Required to achieve compliance to this standard)IEEE Std 1364, IEEE Std 754
Informative References(Provided for Information)IEEE Std 1364:2001, IEEE Std 1364:1995, ISO/IEC 9899:1999, IEEE 100
Replaced ByBS IEC 62530:2011
International RelationshipsIEC 60950-23:2005,IEC 62530:2007,IEC 62530:2011
Draft Superseded By03/103066 DC
DescriptorsComputer programs, Electronic equipment and components, Interfaces (data processing), Syntax, Verification, Data processing, Data representation, Design, Computer hardware, Data, Programming languages, Semantics, Data transfer
ICS25.040.01
35.060
CommitteeEPL/501
ISBN978 0 580 59320 8
PublisherBSI
FormatA4
DeliveryNo
Pages664
File Size7.012 MB
Price£518.00


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