BS EN 60191-6-17:2011 - Mechanical standardization of semiconductor devices. General rules for the preparation of outline drawings of surface mounted semiconductor device packages. Design guide for stacked packages. Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA)

BS EN 60191-6-17:2011

Mechanical standardization of semiconductor devices. General rules for the preparation of outline drawings of surface mounted semiconductor device packages. Design guide for stacked packages. Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA)

Status : Current, Under review   Published : June 2011

Format
PDF

Format
HARDCOPY



IEC 60191-6-17:2011 provides outline drawings and dimensions for stacked packages and individual stackable packages in the form of FBGA or FLGA.




Standard NumberBS EN 60191-6-17:2011
TitleMechanical standardization of semiconductor devices. General rules for the preparation of outline drawings of surface mounted semiconductor device packages. Design guide for stacked packages. Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA)
StatusCurrent, Under review
Publication Date30 June 2011
Normative References(Required to achieve compliance to this standard)IEC 60191-6-5, EN 60191-6-5, IEC 60191-6, EN 60191-6
Informative References(Provided for Information)No other standards are informatively referenced
International RelationshipsIEC TS 63019:2019,IEC 60191-6-17:2011,EN 60191-6-17:2011
Draft Superseded By07/30155531 DC
DescriptorsSurface mounting devices, Electronic equipment and components, Integrated circuits, Standardization, Semiconductor devices, Engineering drawings, Packages, Design, Technical drawing, Drawings, Interchangeability, Dimensions, Designations
ICS01.100.25
31.080.01
Title in FrenchNormalisation mécanique des dispositifs à semiconducteurs. Règles générales pour la préparation des dessins d'encombrement des dispositifs à semiconducteurs à montage en surface. Guide de conception pour les boîtiers emplilés. Boîtiers matriciels à billes et à pas fins et boîtiers matriciels à zone de contact plate et à pas fins (P-PFBGA et P-PFLGA)
Title in GermanMechanische Normung von Halbleiterbauelementen. Allgemeine Regeln für die Erstellung von Gehäusezeichnungen von SMD-Halbleitergehäusen. Konstruktionsleitfaden für gestapelte Gehäuse. Feinraster-Ball-Grid-Array und Feinraster-Land-Grid-Array (P-PFBGA/P-PFLGA)
CommitteeEPL/47
ISBN978 0 580 57621 8
PublisherBSI
FormatA4
DeliveryYes
Pages32
File Size1.414 MB
Price£182.00


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