BS IEC 62142:2005 - Standard for Verilog register transfer level synthesis

BS IEC 62142:2005

Standard for Verilog register transfer level synthesis

Status : Withdrawn   Published : December 2005

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Defines a set of modeling rules for writing Verilog® HDL descriptions for synthesis. Adherence to these rules guarantees the interoperability of Verilog HDL descriptions between register-transfer level synthesis tools that comply to this standard. The standard de.nes how the semantics of Verilog HDL are used, for example, to describe level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.




Standard NumberBS IEC 62142:2005
TitleStandard for Verilog register transfer level synthesis
StatusWithdrawn
Publication Date05 December 2005
Withdrawn Date04 June 2010
Normative References(Required to achieve compliance to this standard)IEEE Std 1364:2001
Informative References(Provided for Information)No other standards are informatively referenced
International RelationshipsIEC 62142:2005
DescriptorsComputer hardware, Data, Data processing, Data representation, Data transfer, Computer systems configuration, Programming languages, Interfaces (data processing), Computer programs, Programming instructions, Semantics, Syntax
ICS25.040.99
35.060
CommitteeEPL/501
ISBN0 580 46457 1
PublisherBSI
FormatA4
DeliveryNo
Pages112
File Size750 KB
NotesThis standard has been withdrawn as IEC 62142:2005 has been withdrawn.
Price£292.00


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