BS EN 61523-2:2002 - Delay and power calculation standards. Pre-layout delay calculation specification for CMOS ASIC libraries

BS EN 61523-2:2002

Delay and power calculation standards. Pre-layout delay calculation specification for CMOS ASIC libraries

Status : Withdrawn   Published : September 2002

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Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.




Standard NumberBS EN 61523-2:2002
TitleDelay and power calculation standards. Pre-layout delay calculation specification for CMOS ASIC libraries
StatusWithdrawn
Publication Date27 September 2002
Withdrawn Date31 August 2014
Normative References(Required to achieve compliance to this standard)No other standards are normatively referenced
Informative References(Provided for Information)No other standards are informatively referenced
International RelationshipsEN 61523-2 (IEC 61523-2:2002),IEC 61523-2:2002
DescriptorsMetal oxide semiconductors, Electronic engineering, Semiconductors, Integrated circuits, Computerized control
ICS31.200
35.240.50
Title in FrenchCalcul de puissance et de delai. Specification du calcul du delai de pre-implantation pour les librairies ASIC CMOS
Title in GermanBerechnung von Verzoegerung und Leistungsaufnahme beim Entwurf von Chips. Vorgezogene Berechnung der Verzoegerung fuer CMOS-ASIC-Bibliotheken
CommitteeEPL/501
ISBN0 580 40460 9
PublisherBSI
FormatA4
DeliveryNo
Pages42
File Size946 KB
NotesThis standard has been withdrawn without replacement as the corresponding European standard has been withdrawn by CENELEC.
Price£218.00


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